Fast-switching current sources are found in high-speed digital-to-analog converters (DACs) used in a variety of applications, such as video display devices. Desirable qualities in these fast-switching current sources are, for example, low susceptibility to noise and short switching times.
FIG. 1 shows a DAC current source circuit 100 known in the art. As shown in FIG. 1, circuit 100 comprises PMOS transistors 101-104. In circuit 100, the gate terminals of transistors 101 and 102 are connected in common and are biased by the voltage at the drain terminal of transistor 101. The current in the drain terminal of transistor 101 is constrained by a current reference signal IREF. The source terminals of transistors 101 and 102 are connected to the power supply VDD, typically 5 volts. Transistor 102's drain terminal is connected to the source terminals of transistors 103 and 104 at node 105. The gate terminals of transistors 103 and 104 are respectively provided the input signal SELECT and voltage reference signal VREF. The output current IOUT of the DAC current source circuit 100 is provided by the drain terminal of transistor 103.
The operation of circuit 100 can be understood by noting that a transistor's current in its source and drain terminals can be approximated by the equation: EQU I=0.5 B*(V.sub.1 -V.sub.t).sup.2,
where
B is a parameter dependent upon the fabrication process and the dimensions of the transistor; PA1 V.sub.1 is the voltage difference between the gate and source terminals of the transistor; and PA1 V.sub.t is the threshold voltage of the transistor.
Since the threshold voltage V.sub.t and the parameter B are set by the fabrication process and does not normally vary during transistor operation, the voltage difference V.sub.1 between the gate and source terminals of transistor 101 can be controlled by the current reference signal IREF. Because the gate terminals of transistors 101 and 102 are commonly connected, and both source terminals of transistors 101 and 102 are connected to the supply voltage VDD, the current in the source and drain terminals of transistor 102 can be maintained substantially constant by maintaining the current reference signal IREF constant. As a result, the bias voltage generated at the gate terminal of transistor 102 is also maintained constant. If the sizes of transistors 101 and 102 are substantially the same, PMOS transistor 101 and 102 form a "current mirror," in which a current substantially equal to IREF can be made to flow in the source and drain terminals of transistor 102. This constant current in transistor 102 is "steered" into one of the transistors 103 and 104 by the input signal SELECT, which can assume either a low voltage state or a high voltage state. An alternative method to achieving the same substantially constant current in the source and drain terminals of transistor 102 connects a suitable reference voltage source at the gate terminal of transistor 102, instead of using current mirror transistor 101 and the reference current IREF.
When the SELECT signal transitions to the low voltage state (i.e. circuit 100 is in the "nonactive mode"), transistor 104 operates at its saturation region (i.e. low impedance), and in turn, pulls the voltage at node 105 down to a voltage determined by the size of transistor 104. This non-active mode voltage at node 105 is designed not to exceed the voltage reference signal VREF by the threshold voltage V.sub.t. As a result, transistor 103 is turned off when circuit 100 is in the non-active mode. Hence, the SELECT signal steers transistor 102's substantially constant current into transistor 104, resulting in only a very little amount of leakage current in the output current signal IOUT. A suitable value for the voltage reference signal VREF is 1.2 volts, which provides a high output impedance at the source terminal of transistor 103.
Conversely, when the SELECT signal transitions to the high voltage state, such as supply voltage VDD (i.e. circuit 100 is in the "active mode"), transistor 104 is turned "off" (i.e. high impedance), so that the voltage at node 105 rises. Circuit 100 is designed such that the voltage at node 105 rises sufficiently to turn on transistor 103, to cause transistor 102's substantially constant current to flow as the output current IOUT through the source terminal of transistor 103. In other words, the impedance across the source and drain terminals of transistor 104 when the SELECT signal is at supply voltage VDD is higher than the output impedance of transistor 103.
While circuit 100 is widely used, circuit 100 has a significant disadvantage, which results from the presence of parasitic capacitors in transistor 104. One such parasitic capacitor is the gate-to-source capacitor modelled by capacitor C.sub.1 of FIG. 2, which shows circuit 100 with capacitor C.sub.1 explicitly drawn to illustrate its effect. In practice, the capacitance of capacitor C1 is in the order of 0.2 pf.
When circuit 100 is in the non-active mode, the voltage difference between node 105 and the gate terminal of transistor 104 can be as much as 3 volts. However, as circuit 100 transitions to the active mode, i.e. signal SELECT transitions from ground voltage to the supply voltage VDD and, in the process, turning off transistor 104, the charge on capacitor C1 causes node 105 to overshoots momentarily the active mode steady-state voltage of node 105, causing a "current spike" in the output current signal IOUT during each transition. In many DAC designs, this current spiking effect is especially pronounced because the output currents of more than one current sources are combined. In such designs, current spikes in the commonly connected output signals of these current sources can occur simultaneously, resulting in a cumulative effect which can be detrimental to the quality of reference signals in the integrated circuit, such as the ground plane, and VREF.
Therefore, it is highly desirable to have a DAC current source which is not susceptible to the current spikes discussed above.